· Executable third-generation simulation platform based on multi-core parallel computing, a new member of the industry-leading Cadence Verification Suite family
· Single core simulation performance increased by an average of 2 times
· Based on existing servers, the performance of multi-core simulation is 3 times, 5 times, and 10 times faster in RTL design simulation, gate level simulation and DFT simulation respectively.
On March 1, 2017, Shanghai – Haodeng Electronics (Cadence, NASDAQ: CDNS) today announced the industry's first third-generation parallel simulation platform, XceliumTM, which has been streamed through the product. Based on multi-core parallel computing technology, XceliumTM can significantly reduce the time to market for system-on-a-chip (SoC). Compared with Cadence's previous generation simulation platform, the performance of XceliumTM single-core version can be increased by 2 times on average, and the performance of multi-core version can be increased by more than 5 times. The Cadence® Xcelium simulation platform has been successfully applied to early adopters in mobile, imaging, server, consumer electronics, Internet of Things (IoT) and automotive applications, and has been streamlined for product verification. For more information, please refer to.
“Either ARM or our partners, delivering products to meet customer expectations, inevitably requires fast and rigorous verification,†said Hobson Bullman, General Manager, Technical Services Products, ARM. “The Xcelium Parallel Simulation Platform is based on ARM's SoC design achieves a 4x performance improvement in gate-level simulation and a 5x performance improvement in RTL simulation. Based on these results, we expect Xcelium to help us deliver the most complex SOC faster and more reliably,"
“For complex 28nm FD-SOI SoC and ASIC designs in smart car and industrial IoT applications, fast and scalable simulation is key to meeting the demanding development cycle!†said Francois Oswald, CPU team manager at STMicroelectronics, “ We used the Cadence Xcelium parallel simulation platform to achieve an 8x speed increase in serial mode DFT simulation, so the digital and mixed-signal SoC verification team chose Xcelium as the standard simulation solution."
The Xcelium simulation platform has the following advantages to greatly accelerate system development:
· Multi-core simulation, optimize running time and speed up project progress: The third-generation Xcelium simulation platform is derived from the acquisition of the technology brought by RockeTIck, and is the only parallel simulation platform based on product streaming in the industry. With Xcelium, execution time can be significantly reduced, with an average speed of 3 times in register transfer level (RTL) simulation, 5 times in gate level simulation, 10 times in DFT simulation, and weeks to months.
· Wide range of applications: The Xcelium simulation platform supports a variety of new design styles and IEEE standards, enabling engineers to improve performance without recoding.
· Easy to use: The compilation process of the Xcelium simulation platform distributes the design and verification test environment code to the optimal engine, and automatically selects the optimal number of CPU cores to improve execution speed.
· Increased productivity with multiple patented technologies (in application): New technologies to optimize overall SoC verification time include SystemVerilog Testbench coverage and multi-core parallel compilation for fast verification convergence.
“Verification is often the most costly and time-consuming part of designing and developing high-quality new products,†said Dr. Anirudh Devgan, senior vice president and general manager of the Digital Sign-Off Division and System Verification Division at Cadence. "The Xcelium Simulation Platform, JasperGold® Apps, Palladium® Z1 Enterprise Simulation Platform and ProTIumTM S1 FPGA Prototyping Platform together form the most powerful suite of verification products on the market, helping engineers accelerate design innovation."
The new Xcelium simulation platform is a new member of the Cadence Verification Suite family, inheriting Cadence's innovative heritage and fully compliant with the Cadence System Design Implementation (SDE) strategy, which is designed to help systems and semiconductor design companies develop more complete and better. Competitive end products. The Cadence VerificaTIon Suite includes state-of-the-art core engine technology that uses a variety of verification architecture technologies and solutions to help customers optimize design quality, increase productivity, and meet verification needs in different applications and verticals.
Cadence also announced the ProTIum S1 FPGA Prototyping Platform, a new member of the Cadence Verification product family, with prototype verification time reductions of up to 50%. To learn more about the Protium platform, please visit S1.
About 楷登电åCadenceCadence is committed to driving electronic systems and semiconductor companies to design innovative end products that change the way people work, live and play. Customers use Cadence's software, hardware, IP and services to cover semiconductor chips to board design and the entire system, helping them deliver products to the market faster. Cadence's innovative "system design implementation" strategy will help customers develop more differentiated products, whether in mobile devices, consumer electronics, cloud computing, automotive electronics, aerospace, Internet of Things, industrial applications, and other applications. . Cadence was also selected by Fortune Magazine as one of the “100 Best Companies to Work for in the World of the Yearâ€. To find out more, please visit the company website.
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