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Abstract: The ADV7183 is an enhanced video decoder with an integrated 10-bit ADC from Analog Devices, Inc. (ADI). It includes two 10-bit precision analog-to-digital converters (ADCs) and a complete automatic gain control (AGC) circuit that can be used in many systems such as projectors, digital TVs, DVD recorders and game consoles. The structure, pin function and working principle of the structure are introduced in detail, and its typical application circuit is given.Keywords: video decoder; line-locked system clock (LLC); analog-to-digital converter (ADC); ADV7183
1 Overview
The ADV7183 is a comprehensive video decoder. It automatically converts an analog video baseband signal compatible with international standard NTSC or PAL into another YCrCb type 4:2:2 or 4:1:1 video data compatible with 16-bit/8-bit CCIR601/CCIR656. Its flexible digital output interface enables video decoding and conversion in a buffer-based and line-locked clock-based system, making the ADV7183 widely available in a wide range of systems including projectors, digital TV, DVD recorders and gaming consoles. The main features of ADV7183 are as follows:
â— Internal with line lock system clock (LLC) and adaptive digital line length tracking (ADLLT) circuit, can provide dual video lock function;
â— has a three-line chroma comb filter;
â— With real-time clock and information output function;
â— With complete AGC and clamp control function, programmable video adjustment for chromaticity, brightness, saturation and contrast;
â— There are 6 analog video input channels;
â— Can be set to 2-wire continuous bidirectional port mode and compatible with I2C?
â— Automatic NTSC or PAL detection;
â— Video input with different modes and 16-bit width bus digital output;
â— The input peak-to-peak value is 0.5V to 2V.
figure 1
2 pin function
The pinout of the ADV7183 is shown in Figure 1 (top view). It is available in an 80-LQFP package. The pins are defined as follows:
(VS/VACTIVE) 1 pin: Dual function multiplexed pin, when (OM_SEL[1:0]=0, 0)? This pin outputs the vertical sync signal VS corresponding to the YUV pixel data; and when (OM_SEL[1 When :0]=1, 0 or 0,1), VACTIVE is a valid signal during the valid period of the video field.
(HS/HACTIVE) 2 pin: Dual function pin (when (OM_SEL[1:0] = 0, 0), the output is a programmable line sync signal HS; and when (OM_SEL[1:0]=1 , 0 or 0,1), HACTIVE is a valid signal during the validity of the video line.
(DVSSIO) 3, 14: Digital input / output ground.
(DVDDIO) 4, 15 feet: Digital input / output power supply? 3.3V?.
(P15 ~ P0) 5 ~ 8, 19 ~ 24, 32, 33, 73 ~ 76 feet: video pixel output port, including 8bit brightness signal Y (P15 ~ P8) and 8bit color difference signals Cb and Cr (P7 ~ P0) .
(DVSS1~3) 9, 31, 71: Digital power ground.
(DVDD1~3) 10, 30, 72 feet: Digital power supply pin (3.3V).
(AFF) 11 feet: almost full sign. When the FIFO reaches the almost full edge set by the user, the pin is a FIFO control signal indicator.
(CLKIN) 16-pin: Asynchronous FIFO clock.
(LLCREF) 25 feet: clock reference output.
(GPO[3:0]) 17, 18, 34, 35: General purpose output controlled by I2C.
(LLC2) 26-pin: The line-locked system clock output is divided by two (13.5MHz).
figure 2
   (LLC1/PCLK) 27-pin: Dual function multiplexed pin? Line lock system clock output or 20 to 35 MHz FIFO output clock.
(XTAL1) 28: The second pin of the crystal oscillator. If an external clock source is used, the pin can be disconnected.
(XTAL) 29-pin: 27MHz crystal oscillator input pin or input to an external crystal oscillator (compatible with CMOS levels).
(PWRDN) 36 feet: low power enable.
(ELPF) 37 pin: This pin is mainly used for the external loop filter necessary for the LLC phase-locked loop.
(PVDD) 38 feet: power supply.
(PVSS) 39 feet: ground.
(AVSS) 40, 47, 53, 56, 63 feet: analog power ground.
(AVSS1 to 6) 41, 43, 45, 57, 59, 61: Analog input channel. If single terminal mode is selected, grounding? When a different mode is selected, it is directly connected to REFOUT.
(AVDD) 50 pin: Analog power pin (5V).
(CAPY1-2) 48, 49 feet: ADC capacitor network.
(SDATA) 67 feet: MPU port serial data input/output.
(REFOUT) 51 pin: Internal reference voltage output.
(CML) 52 feet: ADC common mode.
(SCLK) 68 pin: MPU port serial clock input interface.
(CAPC1~2) 54, 55 feet: ADC capacitor network.
(ALSB) 66 feet: TTL address input.
(ISO) 65 feet: Input exceeds the switch.
(AIN1 ~ 6) 42, 44, 46, 58, 60, 62 feet: analog video input channel.
(VREF/VRESET) 69 feet: VREF marks the beginning of the next game; VRESET marks the beginning of the new field.
(HREF/HRESET) 70 feet: HREF marks the beginning of a new video line; HRESET marks the beginning of a new line.
(RD) 77 pin: Asynchronous FIFO read enable signal.
(RESET) 64 feet: System input reset.
(DV) 78 pin: Data valid output signal.
(OE) 79: Output enable control port.
(FIELD) 80 feet: odd/even field output signal.
3 Working principle
The internal principle and functional block diagram of ADV7183 is shown in Figure 2. The working principle is described below.
3.1 Analog signal input
The ADV7183 has six analog video input channels. These six channels can support six CVBS input signals, three S-video input signals, and two YCrCb analog video input signals in different configurations. The type of input and the choice of channel can be controlled by INSEL. The analog signal input front end includes three clamp circuits for DC recovery. There are three sample-and-hold amplifiers in front of the ADC that guarantee the sampled value to reach three channels simultaneously in the YCrCb input mode. Two 10-bit ADCs are used for sampling. In order to capture video signals with the highest possible quality, there is a big difference in the front end of the entire analog signal input.
3.2 Synchronous pixel output interface
The ADV7183 supports three output interface modes: LLC-compatible sync pixel interface, CAPI interface, and SCAPI interface. When set to the sync pixel interface mode, the output of the pixel and control data is synchronized with LLC1 (8-bit mode) or LLC2 (16-bit mode). Field blanking, line blanking, and column blanking control and timing information encoding are the same as control codes in this mode. When set to CAPI interface or SCAPI interface mode, only the activated pixel data output is synchronized with the asynchronous first in first out clock (CLKI). Pixels are typically output through a 512-pixel deep, 20-bit wide FIFO container. HACTIVE and VACTIVE outputs typically use separate pins. The interface mode data of the CAPI interface and SCAPI is always 16-bit. Therefore, when the output interface requires 8-bit or 10-bit, this interface mode cannot generally be used. The default mode of the ADV7183 is an 8-bit CCIR656 4:2:2 compatible with LLC.
Figure 4
   3.3 Control and pixel interface FIFO mode
Figure 3 shows the control and pixel FIFO interface mode timing of the ADV7183. When the ADV7183 is operating in this mode, the resulting pixel data is buffered in a 512-pixel deep FIFO container. Only activated video pixels and control codes are written to the FIFO, and the rest are discarded. In this mode, CLKIN must be faster than the effective data rate shifted into the FIFO, otherwise the FIFO will overflow. When the ADV7183 is operating in SCAPI interface mode, a feedback system from DV (data valid) to RD (read enable) can be used to ensure that the FIFO does not overflow. When the FIFO reaches the AFF (almost full flag), the DV rises immediately and keeps the FIFO as an AEF (almost empty flag). When using this mode, the data status of the output pixels can be determined by the DV and QCLK indicators.
4 Typical applications
Figure 4 shows a typical application circuit for the ADV7183. The supply voltage VAA of the circuit should be selected as 7V, VDD should be selected as 4V, the digital input pin voltage should be GND-0.5V to VAA+0.5V, and the analog output voltage should be GND-0.5V to VAA. The circuit can operate in the temperature range of 0 to 70 °C. Also note that the ADV7183 is an ESD (electrostatic discharge)? Although the ADV7183 itself has an ESD protection circuit, the ADV7183 can cause performance degradation and functional degradation due to continuous damage from high-intensity electrostatic discharge, so it is necessary to take appropriate ESD protection measures.
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