This article refers to the address: http://
Abstract: SAA7185 is a digital video encoder with 10-bit DACs from PHILIPS. It combines D/A and encoding in one, and can encode and D/A convert the input 16-bit YUV mode, CCIR656 format and MPEG format. Digital to analog conversion?, to output PAL system, NTSC system Composite video signal (CVBS) or S-Video mode Y/C component signal and composite full TV signal. Therefore, the SAA7185 can be widely used in many systems such as VCD DVD players, projectors and digital TVs. The structure, pin function and working principle of the structure are introduced in detail, and its typical application circuit is given.Keywords: digital video encoder; SAA7185; D/A conversion
1 Overview
The SAA7185 is a multi-function digital video encoder from PHILIPS. It can receive 16/8bit 4:2:2 YUV format, CCIR656 format or 8bit MPEG format video data and encode it into PAL format, NTSC composite video signal (CVBS) or S-Video mode Y. /C component signal and composite full TV signal. The SAA7185's advanced height flexibility and multiple input and output interface features enable a wide range of conversions, making the SAA7185 widely available in many VCD DVD players, projectors and digital TVs. Its main features are:
â— is a digital PAL/NTSC TV standard encoder;
â— With 8bit MPEG and 16bit YUV input ports;
â— Optional I2C bus or MPU parallel control mode;
â— The encoder has two working modes: master and slave;
â— Input line, field sync and output line sync phase are programmable;
   ◠It can control the rise/fall time of the output sync signal and the blanking signal;
â— It can simultaneously output composite video signal (CVBS) and S-Video Y/C component signals and composite full TV signals.
2 pin function
The pinout of the SAA7185 is shown in Figure 1 (top view). It is available in a PLCC68 package. The function and description of each pin are listed in Table 1.
Table 1 Pin Function Description of SAA7185
| Pin | Name | I/O/P/G | Function description |
| 1,8,19,28,35,42,62 | VSSD1-7 | G | Digitally |
| 2 to 5 | DP4～7 | I/O | The upper 4 bits of the data port. If pin 68 (SEL-MPU) is high, these ports are parallel MPU data bus interfaces; otherwise, they are the UV data ports of the video data. |
| 6 | RCV1 | I/O | Video raster control port 1. Depending on the sync mode, this pin receives or provides a VS/FS/FSEQ signal. |
| 7 | RCV2 | I/O | Video raster control port 2. Depending on the sync mode, this pin receives or provides a VS/HREF/CBL signal. |
| 9 to 16 | VP0~VP7 | O | Video port. Compatible with input video data in CCIR 656 format. If you input data in 16-bit DIG-TV2 format, they are Y data input ports. |
| 17,37,67 | VDDD1-3 | P | Digital power supply |
| 18 | SEL-ED | I | Select the input data of the decoder, from the MPEG port or video port |
| 20~27 | MP7～MP0 | I | MPEG port. Is a multiplexed YUV data input port that supports CCIR 656 format |
| 17,37,67 | VDDD1-3 | P | Data supply |
| 18 | SEL-ED | I | Select the input data of the decoder, from the MPEG port or video port |
| 2027 | MP7MP0 | I | MPEG port. Is a multiplexed YUV data input port that supports CCIR 656 format |
| 29 | RCM1 | I | MPEG raster control port 1. This pin provides a VS/FS/FSEQ signal |
| 30 | RCM2 | I | MPEG raster control port 2. This pin provides an HS signal |
| 31 | KEY | I | The key signal of the OSD. Highly effective |
| 3234 | OSD0-2 | O | Index of the internal OSD query table |
| 36 | CDIR | I | Clock direction. If CDIR is high, the circuit receives the clock signal. Otherwise, both the LLC and CREF signals are generated by the internal crystal oscillator. |
| 38 | LLC | I/O | Row lock clock |
| 39 | CREF | I/O | Clock reference signal |
| 40 | XTALO | O | Crystal output |
| 41 | XYALI | I | Crystal input. If not used, the pin should be grounded |
| 43 | RTCI | I | Real-time control input |
| 44,45 | AP, SP | I | Test pin |
| 46,47 | VREFL, VREFH | P | Low reference voltage input and high reference voltage input for DAC |
| 48,50,54,56 | VDDA1-4 | P | Analog power supply |
| 49 | CHROMA | O | Analog output of chrominance signal |
| 51 | Y | O | Analog output of luminance signal |
| 52 | VSSA | G | Analog ground of DAC and output amplifier |
| 53 | CVBS | O | Analog output of CVBS signal |
| 55 | II | I | Current input of the output amplifier |
| 57 | RESET | I | Reset input |
| 58 | DTACK | O | Data response output of the parallel MPU interface. Low effective; otherwise, high resistance |
| 59 | RW/SDA | I/O | If pin 68 (SEL-MPU) is high, this pin is the address signal of the MPU interface; otherwise, it is the serial data input/output of the I2C bus. |
| 60 | A0/SDA | I/O | If pin 68 (SEL-MPU) is high, this pin is the address signal of the MPU interface; otherwise, it is the serial data input/output of the I2C bus. |
| 61 | CS/SA | I/O | If pin 68 (SEL-MPU) is high, this pin is the chip select signal of the MPU interface; otherwise, the pin is selected for the sub address of the I2C bus. |
| 63~66 | DP0~DP3 | I | If pin 68 (SEL-MPU) is high, this is the lower 4 bits of the data bus of the parallel MPU interface; otherwise, the UV data for the video data |
| 68 | SEL-MPU | I | If it is high, the parallel MPU interface is valid; otherwise, the I2C bus interface is valid. |
3 Working principle
The internal functional block diagram of SAA7185 is shown in Figure 2. The working principle is described below.
3.1 Input of data
MPEG-compatible SAA7185 digital video decoder can encode digital luminance and chrominance signals into analog CVBS (composite video signals), and can also encode them into S-Video signals (Y/C separated component signals and composite full TV signals) ). The digital-to-analog converter (DAC) in the device has 10-bit resolution, and the encoder provides three 8-bit wide data ports to suit different applications. Both MPEG port (MP) and video port (VP) can receive composite YcrCb data. The video port (VP) can also handle 16-bit YUV signals compatible with the DIG-TV2 series, where the data port (VP) is used for U/V signals. In addition, the data port can also be used as a microprocessor interface with an 8-bit data width.
3.2 output interface
On the output interface, the encoded Y and C signals are converted from digital signals to analog signals with 10-bit resolution, while the Y and C signals are also combined into 10-bit CVBS signals. Prior to synthesis, the luminance signal is sent to a deeper level of the filter to suppress subcarriers in the signal. This reduces color distortion, which is very beneficial for televisions with standard CVBS signal inputs. The slope of the sync pulse is not affected by any effective color distortion. The output CVBS signal and the Y and C signals have the same processing delay. The output voltage of the digital-to-analog converter (DAC) can be set to the minimum output voltage by software to meet specific needs.
figure 2
   3.3 Synchronization
The encoder can work in both master and slave modes.
In slave mode, the circuit receives a sync pulse on the bidirectional port RCV1. The timing and trigger characteristics associated with the video signals of VP (and DP) can be changed by programming the polarity and on-chip delay of RCV1. If the horizontal phase is not affected by RCV1, the horizontal phase can be provided by the RCV2 pin, and the timing and trigger characteristics can also be changed by RCV2. If the vertical and horizontal pulses are from RCV1, RCV2 can be used for horizontal or composite blanking inputs or outputs.
In master mode, the time base of the circuit can run continuously freely. On the RCV1 port, the IC can output a field sync signal (VS) with 2.5 or 3 line delay, odd/even field signal (ODD/EVEN), or field sequence signal (FSEQ). On the RCV2 port, the IC can Programmable start and end horizontal phases are provided. The output pulse phase of the RCV1 or RCV2 port is related to the VP port, and the polarity of both signals is selectable.
3.4 Control Interface
The SAA7185 has two control interfaces: an I2C bus interface and an 8-bit parallel microprocessor interface. The I2C bus interface is a standard slave transceiver that supports 7-bit slave address and 100kbits/s transmit rate. It has an 8-bit subaddress with auto-increment. With the exception of one readable status word, all other registers can only be written.
   The parallel interface consists of two registers, one with a self-incrementing function that contains the current address of the control register. The other contains actual data. The current address register can be mapped to the corresponding control register. The status word can only be read freely through a read channel to the address register, and no other read channels are provided.
4 Typical applications
Figure 3 shows an application circuit of the SAA7185. The analog and digital power supplies of the circuit are both 5V. The circuit is a digital encoding circuit commonly used in VCD DVD players and multimedia movie decompression cards. The input data in the system can be 16-bit YUV mode or CCIR656 format. The input is 8-bit MPEG-1 data, which is compatible with CCIR656. In this system, the SAA7185 encoder operates in master mode.
This series is LED wireless battery par light, the wireless design makes it more portable, the chassis design is compact, the weight is moderate, and it is convenient to transfer in the place. In addition to the traditional DMX signal control, the convenient mobile app control has become a more convenient control method, and the color and brightness are not inferior to conventional par lights. Equipped with a flight case with a socket, it is convenient to charge the lamp anytime and anywhere, and it can be taken out for use when it arrives at the destination, and it can be used for 24 hours after being fully charged.
Wireless Battery Par Lights ,Wireless Battery Par Lights,Wireless Led Par,Wireless Led Par Lights
Guangzhou Cheng Wen Photoelectric Technology Co., Ltd. , https://www.leddisplaycw.com