Many people think that hardware accelerators are nothing more than a faster emulator. Undoubtedly, because hardware accelerators use physical hardware for simulation, using hardware accelerators to verify complex integrated circuits and large system-on-chip (SoC) can be orders of magnitude faster than software simulators. Compared to general-purpose computers for simulation, simulations use single-function computers to provide higher-capacity, more efficient systems.
And, many companies that own and use hardware accelerators have found that in addition to the ability to speed up simulations, hardware accelerators have other features. For example, many experienced hardware accelerator users are pushing the package for complete end-to-end functional verification, where the end of the design under test is the driver and the other end is the other target peripheral. End-to-end functional testing enables the identification of complete functional paths for large SoCs (including multimedia, PCIe, USB, and Ethernet) before streaming.
The ability to fully validate drivers and hardware is more significant than simply speeding up simulation. This allows for greater availability of system-on-a-chip (SoC) availability due to the use of real drivers and precise hardware peripheral interfaces for debugging on hardware accelerators. At the same time, fully tested device drivers speed up debugging after the film is returned.
In addition, the high speed and large capacity of the hardware accelerator allows the design under test (DUT) to run on the same silicon chip's native environment as the chip, much earlier than the FPGA prototype and samples. The hardware accelerator makes it possible to start the real-time operating system (RTOS), run device drivers, perform complex calculations, send instructions to the DUT, and display the results. As a result, hardware accelerator users can do much more than simulation acceleration, and they can now verify a "virtual" SoC in a silicon environment, doing the same tests as a real chip.
One of the areas in which users have successfully applied this end-to-end verification process is to verify the phone's graphics processing unit (GPU). First, the GPU core is compiled in the hardware accelerator. Then, call the driver. In order to run the driver, the RTOS must be started because the device driver needs to be able to run with the features included in the RTOS. Finally, the GPU renders the image, in other words, the output of the DUT. A series of very complicated operations are involved in the whole process. It takes billions of clock cycles to start LinuxRTOS. The RTOS sends an original image to the device driver. The device driver first performs countless calculations and storage operations on the image, then acquires and provides information such as the storage address to the GPU, and finally instructs the GPU to render the image. The GPU then takes the required data from these addresses for image production. All of these activities require a lot of software to run, and it takes billions of cycles to turn a series of frames into video.
With such a huge number of clock cycles, the software emulator can't be done simply, and the hardware accelerator can. For example, Mentor Graphics' Veloce hardware accelerator can run one million cycles per second, so users can run 10 billion cycles in about two hours. The ability to run the driver on the processor, receive the original image, prepare the image, send the image to the GPU for rendering, and then process it into the final image, which allows the hardware accelerator user to fully test the design under test as well as the final product.
Veloce users also have a unique advantage of displaying GPU-rendered images using the VirtuaLAB multimedia analysis component running on the workstation, which takes multiple frames from the hardware accelerator and combines them into video. This allows Veloce users to see live video, so users can visually check for slow response times, jitter, smearing, ghosting, and more.
Figure 1: The VirtuaLAB Multimedia Analysis component collects and visualizes and visualizes video and audio streams from the design under test running in the Veloce hardware accelerator.
Only Mentor Graphics' Veloce simulation environment can provide such an end-to-end functional verification process, as only Veloce has the supporting technology required for this process. Veloce provides a complete functional verification environment including assertion, feature coverage, low power verification, comprehensive embedded software debug suite, virtual and physical peripherals, virtual probes, accelerated software execution, fast and accurate design compilation, Full-chip debug visibility and enterprise-class server capabilities. Mentor's unparalleled ultra-high-speed data channel enables lightning-to-speed transfer of large amounts of data between the simulator and the workstation, so engineers can debug on hardware accelerators and workstations without interrupting the simulation.
Figure 2: Hardware acceleration technology is becoming more than just speeding up simulation.
Thanks to the combination of drivers, RTOS and GPU, the hardware accelerator-based end-to-end SoC functional verification process provides users with high confidence, because of the full functional verification, the video interface, processor and memory of the aforementioned chip There is little chance of a system malfunction. And since the driver has been fully debugged on the real hardware implemented by the hardware accelerator, once the chip has any problems, the design team will know that the chip has manufacturing problems, so there is no need to waste time re-verifying the GPU or GPU and processing. On the interface of the device, which greatly improves the confidence of the film and the speed of the product.
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