Nowadays, in the embedded processor chip, the processor with ARM7 as the core is one of the more applications. It has multiple modes of operation and supports two different instruction sets (standard 32-bit ARM instruction set and 16-bit Thumb instruction set). μC/OSII is a preemptive, multi-tasking real-time operating system designed for embedded applications and can be used with a variety of 8-bit, 16-bit and 32-bit microcontrollers or DSPs. μC/OSII has unique advantages for ARM7 transplantation. Therefore, “μC/OSII+ARM7†has become a widely used platform.
Regardless of the type of ARM processor and whether there is an operating system in the embedded system, interrupt technology is a key technology in the real-time interaction between the computer and the outside world. When an external event occurs, the CPU must respond to the interrupt in time to handle the corresponding event. Therefore, interrupting nesting is the main factor affecting the real-time performance of the embedded system.
1 ARM7 interrupt processing
There are two main types of interrupts for the ARM7 processor. This article focuses on the response mechanism of IRQ interrupt exceptions. When the interrupt request IRQ comes in and the CPU enters the interrupt response, the CPU will automatically complete the following tasks: First, store the current value of the PC and CPSR in the LR and SPSR of the interrupt mode; then, operate the operation status bit in the CPSR to make The CPU enters the interrupt mode and closes the interrupt; finally, the value of the PC is changed to 0x00000018, so that the execution of the CPU jumps to the IRQ interrupt entry 0x00000018. An "LDR PC, [PC, #-0xff0]" instruction is used at 0x00000018 in the exception vector table. This instruction used at IRQ is different from other vectors. When the CPU executes this instruction but has not yet jumped, the value of the PC is 0x00000020 (because the ARM7TDMI core is a three-stage pipeline structure), 0x00000020 minus 0x00000FF0 is 0xFFFFF030, which is the address unit of VIC's special register VICVectAddr. This register holds the entry to the interrupt service routine of the IRQ currently being serviced, so the value of the VICVectAddr register is read and then placed in the PC program pointer, which jumps to the corresponding interrupt service routine, causing the CPU to start executing the interrupt service routine.
2 Handler macro analysis
In the "μC/OSII+ARM7" system, only the IRQ interrupt of ARM7 is used. Since the interrupt systems of different ARM chips are not exactly the same, it is impossible to write interrupt and clock beat migration codes common to all processors using ARM cores. However, in order to enable the user to write the interrupt service program in C language, it is not necessary to distinguish the hardware of the processor. Here, according to the requirements of the interrupt service program of μC/OSII and the characteristics of ARM7 architecture and ADS compiler, a suitable one is written. All ARM7 core processor-based assembly macros -- Handler. This macro implements a common interface between the assembly language code of the "μC/OSII+ARM7" interrupt service routine and the C language function code. Its function is to wrap the user's C language interrupt handler, and only after passing this package can the system execute the user's interrupt handler.
The interrupt service program flow is shown in Figure 1. In the Handler macro, first save the values ​​of LR, SPSR and related registers in the stack in interrupt mode to facilitate breakpoint recovery. Then, the global variable OSIntNeSTIng, which records the number of system interrupts, is incremented by one and the interrupt is switched to the system mode, and the C language interrupt handler is called. After executing the interrupt handler, the interrupt function is called to get the task control block pointer and task priority of the highest priority ready task. After returning to the interrupt mode, it compares the priority of the current task with the task to be switched, determines whether to perform task switching, and finally returns a breakpoint.
Figure 1 interrupt service program flow
The assembly part of the IRQ exception handling code -- the Handler macro:
MACRO
$IRQ_Label HANDLER $IRQ_ExcepTION_FuncTIon
EXPORT $IRQ_Label; output label
IMPORT $IRQ_ExcepTIon_Function; referenced external label
$IRQ_Label
SUB LR, LR, #4; Calculate the return address
STMFD SP! , {R0-R3, R12, LR}; save the task environment
MRS R3, SPSR; save state
STMFD SP, {R3, SP, LR}^; R3, SP, LR to save user status
;OSIntNesting++
LDR R2, = OSIntNesting
LDRB R1, [R2]
ADD R1, R1, #1
STRB R1, [R2]
SUB SP, SP, #4*3
MSR CPSR_c, #(NoInt | SYS32Mode)
; Switch to system mode to operate on related registers
CMP R1, #1
LDREQ SP, =StackUsr
In the first interrupt, re-open a variable used in the special storage interrupt to avoid storage space conflicts.
BL $IRQ_Exception_Function ; call C language interrupt handler
MSR CPSR_c, #(NoInt | SYS32Mode); Switch to system mode
LDR R2, =OsEnterSum
; OsEnterSum, interrupts when OSIntExit exits
MOV R1, #1
STR R1, [R2]
BL OSIntExit
LDR R2, =OsEnterSum
; interrupt service routine to exit, so OsEnterSum=0
MOV R1, #0
STR R1, [R2]
MSR CPSR_c, #(NoInt | IRQ32Mode) ; Switch back to interrupt mode
LDMFD SP, {R3, SP, LR}^ ; restore user status R3, SP, LR
LDR R0, =OSTCBHighRdy
LDR R0, [R0]
LDR R1, =OSTCBCur
LDR R1, [R1]
CMP R0, R1
ADD SP, SP, #4*3
MSR SPSR_cxsf, R3
LDMEQFD SP! , {R0R3, R12, PC}^ ; no task switching
LDR PC, =OSINTCtxSw; task switching
MEND
END
Through the analysis of the Handler macro, the user's C language interrupt handler runs in the privileged mode-system mode, and the CPU is closed when the interrupt service routine is executed, so the system is the simplest. Non-nested interrupt mode. The advantage of this approach is that the context data is not destroyed by any sequence of interrupts; the disadvantage is that the interrupt can not be nested according to the interrupt priority when the interrupt service routine is executed, and the delay time is long, only when an ISR is completely over and Re-accepting the interrupt after exiting the interrupt reduces the real-time characteristics of the system. In order to improve the real-time performance of the system, it is necessary to optimize its interrupt.
3 interrupt optimization
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